Advantages and disadvantage of 7nm chip

In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nanometer (7 nm) node as the technology node following the 10 nm node. Single-transistor 7nm-scale devices were first produced in the early 2000s; commercial production of 7nm chips is still at a development stage. Most semiconductor production equipment being used for fabrication of 10nm chips are used for 7nm manufacturing. 7nm chips are 10 to 15 percent faster than 10nm chips while reducing power consumption by 35 to 40 percent.

In July 2015, IBM announced that they had built the first functional transistors with 7 nm technology, using a silicon-germanium process.

As of September 2018, mass production of 7 nm devices has begun. The first mainstream 7 nm mobile processor intended for mass-market use, the Apple A12 Bionic, was released at their September 2018 event.

The fundamental flaw with silicon transistors is that at the 7nm point the transistors sit so close to each other that an effect called quantum tunneling occurs. This effect, unfortunately, means that the transistor cannot be turned off reliably and for the most part will stay on. So the physical limitations of silicon are very real and, in fact, insurmountable.

One alternative is to find a material that can physically scale down past silicon or can achieve faster switching speeds.

The new material has higher electron mobility and makes it possible to have faster-switching transistors and lower power requirements. Light is directed onto a mask, which is sort of a stencil of an integrated circuit pattern. Image of that pattern is then projected onto a semiconductor wafer covered with light-sensitive photo-resist. Creating circuits with smaller and smaller features requires shorter and shorter wavelengths of light.

7nm process node technology is expected to have a deeper impact on the vendors involved in businesses such as; semiconductor material/wafer, lithography equipment suppliers, metrology equipment suppliers, device OEMs, design players, and foundry players.

The advantages of improvement in transistor density are –

• Lower power required by transistor switching.

• They have much better performance and reduced power consumption compared to planar transistors.

• Lower power overall.

• Can achieve higher frequency numbers compared to bulk for a given power budget or lower power.

• Less Heat output.

• Less Need for thermal throttling.

• They exhibit more drive current per unit area than planar devices, largely because the height of the fin can be used to create a channel with a larger effective volume but still take advantage of a wraparound gate.

• More space per chip.

• More cores per CPU.

• Larger on-chip cache.

• Space to make architectural improvements.

• Due to reduced need for wide, high-drive standard cells and the ability to operate with a lower supply voltage for a given amount of leakage they have a power reduction.

Disadvantages:

• The major issue is the cost because building a finFET uses a number of additional steps in a manufacturing flow.

• On a bulk-silicon process, control over fin depth is more difficult.

• Pitch splitting involves splitting features that are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.

• Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as ‘pitch walking.

• Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.

• EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures.

• These transistors won’t work because they will be short-circuited if powered.

• At lower nodes, back-end-of-line employs multiple patterning, which requires extra deposition and etching with every pattern, thus increasing the cost of production.

• EUV remains a consistent challenge, and though manufacturers swear they can solve the power problem, the difficulties are staggering.